This relates to digital logic circuitry, and more particularly, to sequential logic circuitry.
A sequential logic circuit receives an input signal, records states of a corresponding system based on the input signal (i.e., in memory), and produces an output signal dependent upon the recorded states of the input signal. The sequential logic circuit typically includes combinational logic and memory circuitry coupled to the combinational logic that records the input signal after the input signal has been acted upon by the combinational logic.
Sequential logic circuits are often used to form digital state machines such as so-called finite state machines that record particular finite states based on the input signal received by the sequential logic circuitry and the combinational logic in the sequential logic circuitry. Finite state machines are typically used as digital logic components in a wide range of digital circuit devices such as memory devices or any other digital devices that rely on the recordation of one or more logical states.
FIG. 1 is a diagram of conventional sequential logic circuitry. As shown in FIG. 1, sequential logic circuitry 10 includes flip flop circuits 12 (i.e., a first flip flop 12-1, a second flip flop 12-2, and third flip flop 12-3). Combinational logic 18 is formed between each pair of flip flops 12 (i.e., first combinational logic 18-1 is formed between flip flops 12-1 and 12-2, whereas second combinational logic 18-2 is formed between flip flops 12-2 and 12-3). Flip flop circuits 12 are clocked using clock signal CLK0 received over clock line 14. Sequential logic circuit 10 receives a data input over line 16. Flip flops 12 in the arrangement of FIG. 1 are rising edge triggered flip flops, such that data bits at an input of a given flip flop are only latched onto the output of that flip flop when a rising edge of clock signal CLK0 is received.
In the arrangement shown in FIG. 1, when clock signal CLK0 is pulsed high, a data bit S0 on input line 16 is latched at the output of flip flop 12-1. Data bit S0 is fed to combinational logic 18-1 which performs combinational logic operations on the bit to generate bit S1 that is provided to an input of flip flop 12-2. When clock signal CLK0 is pulsed high, data bit S1 (i.e., corresponding to bit S0 after being operated on by logic 18-1) is latched onto the output of flip flop 12-2. Data bit S1 is fed to combinational logic 18-2 which performs combinational logic operations on the bit to generate bit S2 that is provided to an input of flip flop 12-3. When clock signal clk0 is pulsed high, data bit S2 is latched to the output of flip flop 12-3. Data bits S0, S1, and S2 are output over lines 20 and collectively define the state of sequential logic circuitry 10 (i.e., a first state of circuitry 10 is defined when S0=0, S1=0, and S2=0, whereas a second state of circuitry 10 is defined when S0=0, S1=0, and S2=1, etc.).
Combinational logic circuits 18-1 and 18-2 each have a given logic depth N (corresponding to the number of logical elements in each logic circuit). Dynamic power used by combinational logic circuits 18 is proportional to the number of logic elements in the circuit (i.e., proportional to the logic depth of the circuit). If care is not taken, combinational logic circuits 18 in circuitry 10 can consume excessive dynamic power for recording a given state. It may therefore be desirable to be able to provide sequential logic circuitry with improved dynamic power consumption.